This invention relates to bipolar transistors which operate at high frequencies, and, more particularly, to a process for fabricating such bipolar transistors having a low parasitic collector resistance.
The conventional processing of bipolar transistors having a collector, base and emitter involves forming a buried N.sup.+ layer, using ion implantation (e.g., an arsenic species) or diffusion (e.g., an antimony species) to achieve a sheet resistance of about 5 to 20 ohms per square in a P.sup.- substrate. An N.sup.- epitaxial layer, doped with phosphorus or arsenic, is then grown to a thickness of about 1 to 5 .mu.m (somewhat thinner for a higher packing density of devices). An isolation layer is formed by diffusing a P.sup.+ region down to the P.sup.- substrate, using, e.g., a boron dopant species, to achieve a sheet resistance of about 30 to 100 ohms per square.
The P.sup.+ isolation region is typically 4 to 7 .mu.m wide and driven to a depth of 3 to 5 .mu.m. Employing this technology limits the spacing between isolated devices to 12 to 20 .mu.m.
In the prior art, a P.sup.+ layer is typically placed away from the device, penetrating 4 .mu.m down and 6 .mu.m wide at the surface. This results in devices spaced 18 .mu.m apart. Employing the process of the present invention permits increasing the packing density to put five devices in the same space occupied by one device in the prior art.
An N.sup.+ region, employing a fast diffuser dopant such as phosphorus, is diffused down to the N.sup.+ buried layer to form the collector contact. The base contact is formed by means of a P-type implant or diffusion, using, e.g., boron as the dopant. The emitter contact is formed with an N.sup.+ diffused region by implantation or diffusion, using, e.g., phosphorus or arsenic, or by forming an N.sup.+ polysilicon layer doped with, e.g., phosphorus or arsenic. Contacts are opened by etching. Resistors are optionally formed as P-diffused regions or as surface thin film devices. Metallization to form connections to the devices typically employs aluminum, aluminum-1% silicon or an aluminum film in conjunction with a refractive metal barrier layer, such as titanium or titanium-tungsten.
Such devices, being diffusion isolated, are large. Trenches have been employed to isolate the devices to reduce the size of the devices. Formation of trenches has typically involved anisotropically etching a trench down to the P.sup.- substrate, using a plasma dry etch such as chlorine plus silicon tetrachloride or chlorine plus carbon tetrachloride. The trenches are then filled and planarized with a dielectric material, such as silicon dioxide, polysilicon or silicon nitride.
The operation of a bipolar transistor at high frequencies requires the device to have a low parasitic collector resistance. One conventional method for reducing the parasitic collector resistance is to form the transistor in a lightly doped epitaxial layer that has been grown over a heavily doped buried layer. Although this is effective in reducing the collector parasitic resistance, the defect density associated with grooving an epitaxial layer potentially prohibits the fabrication of integrated circuits with large numbers of transistors.
A second method of achieving a low collector parasitic resistance uses a high energy implanted buried layer. However, this method also has a potential problem of defects generated during the implantation. Further, it is difficult to maintain a sufficiently low dopant concentration in the region of the base junction unless a very high energy (1 to 3 MEV) is used to implant the buried layer.
One final method of achieving a low parasitic collector resistance that does not use a buried layer is described in U.S. Pat. No. 4,044,452. After etching a trench around the perimeter of a transistor, the bottom of the trench is implanted with an N.sup.+ dopant. Diffusion of the dopant forms a buried layer similar to the process described in the present patent application. However, the lateral diffusion of the dopant requires the spacing between adjacent isolated transistors to be nearly the same as a conventional device having a buried layer. Therefore, this method of achieving a low parasitic collector resistance does not lend itself to building high device density integrated circuits.
Thus, a need remains for a process for providing a bipolar transistor with a low collector resistance and a low defect density, together with a high device packing density.